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TILE64 as replacement for DSP and FPGA Edit

* http://www.theregister.co.uk/2007/08/20/tilera_tile64_chip/

Tilera looks to go after the FPGAs and DSPs used today in embedded devices, claiming performance, performance per watt and programming edges over rivals. See http://www.bdti.com/bdtimark/ofdm. For example, Tilera expects its chip to appear in security appliances that want to handle more-detailed analysis on packets, routers, surveillance DVRs (digital video recorders), video conferencing systems and boxes for encoding high definition video.

Tilera Multicore Edit

Tilera multicore design replaces FPGA and DSP cores.

* http://scratchpad.wikia.com/wiki/TileraMulticore
* http://www.design-reuse.com/news/19119/multicore-processor.html
* http://en.wikipedia.org/wiki/TILE64
* http://en.wikipedia.org/wiki/Tilera
* http://arstechnica.com/articles/paedia/cpu/MIT-startup-raises-multicore-bar-with-new-64-core-CPU.ars
* http://hardware.slashdot.org/article.pl?sid=07/08/20/1830221
* http://linuxdevices.com/news/NS4811855366.html
* http://www.tilera.com/ Used for LTE, Wimax baseband programming
* http://www.jumpgen.com/product/t6m100_amc_tilera_64_core_tile64_processor_card/ 
* http://www.tilera.com/solutions/digital_baseband.php

Register article Edit

* http://www.theregister.co.uk/2008/09/23/tilera_cpu_upgrade/page2.html

That's another way of saying performance is nearly double, and on real workloads, it's somewhere between a factor of 1.5 to 2.5 better than the first Tile64 chips. Significantly for Tilera's marketing efforts, the new TilePro64 running at 866 MHz has 35 times the performance per watt of a 3 GHz quad-core Xeon processor from Intel and 15 times the performance of Texas Instruments' DaVinci DSPs.


Implement Wimax and LTE Edit

http://www.tilera.com/solutions/digital_baseband.php

The current architecture for base stations fall short of delivering the performance, the low latency and the flexibility customers need. To meet the requirements, wireless equipment providers design complex systems with FPGA, ASIC, DSP and processors with each component requiring special tools in a customized development environment. This leads to a long development cycle, sometimes years, before applications can be productized. Changes in standards also impact providers because such systems are inflexible-upgrades can be a slow and expensive process.

What providers seek is an uncomplicated, well-designed, architecture that yields good performance. Tilera's processors provide a low latency single solution that integrates many functions seamlessly in a single processor and uses C/C++ to program their applications with industry standard tools. The familiar tools enable customers to preserve their software investments, replace a number of disparate programming methodologies with one standard programming environment, and gain the flexibility they need to support evolving protocols and ever-increasing demands for service


Tilera Wimax vs. FPGA Wimax Edit

http://www.tilera.com/news_&_events/press_release_080916.php

he Tilera tools and C/C++ programming model enabled completion of the benchmark in weeks as compared to the months it can take on FPGAs and other multicore processors.

SAN JOSE, Calif., September 16, 2008 -Tilera® Corporation, developer of the breakthrough TILE™ family of high-performance processors for the embedded market, today announced that Berkeley Design Technology, Inc. (BDTI) has certified the Tilera TILE64™ as the highest performance embedded processor on its BDTI Communications Benchmark (OFDM)™, an application-oriented benchmark based on an orthogonal frequency-division multiplexing (OFDM) receiver. BDTI has confirmed that the TILE64 delivers up to 10X better performance than high-end digital signal processors. The TILE64 running at 866 MHz is able to process 15 channels of BDTI's OFDM benchmark, the highest number ever recorded for a processor.

This benchmark demonstrates the Tile architecture's versatility in providing high performance in signal processing applications in addition to its already proven performance in general compute applications. Coupled with the Tilera tools suite, the performance provided by the architecture is easily achievable for a variety of signal processing markets such as multimedia and wireless infrastructure equipment.

The BDTI benchmark was implemented in C/C++ with a limited number of intrinsics and without any assembly code. The Tilera iMesh™ network and homogenous cores enabled developers to optimize the benchmark on one core and then replicate the exact code onto the others; as a result, the performance scaled linearly as more cores were added. The Tile processors give customers the flexibility they need by allowing them to implement their own algorithms or use standard off-the-shelf software while still obtaining high performance.

"Achieving these breakthrough BDTI benchmark results in just weeks demonstrates Tilera's ability to provide high performance without sacrificing ease of use or time to market," said Rao Gattupalli, vice president of Applications, Tilera Corporation. "Tilera's easy-to-use programming enables customers to leverage their existing software investment and continue to differentiate themselves in their markets."

The TILE64 processor on the BDTI benchmark surpassed all previously benchmarked processors, providing up to 10X the performance of typical high-end DSPs. Customers using the TILE64 can implement a complete wireless platform integrating signal processing and general compute functions all in one device. This provides customers with significant benefits:

   * the ability to replace a disparate set of tools and programming models with industry-standard tools and standard C/C++ programming;
   * the simplification of platform designs, reducing risk and time-to-market;
   * and an increase in platform compute density, adding more performance per square inch to accommodate growth.

The complete benchmark results can be viewed at www.bdti.com/bdtimark/ofdm. More information on Tilera and the TILE64 processor can be found at www.tilera.com.

About Tilera

Tilera Corporation is the industry leader in highly-scalable general purpose multicore TILE™ processor family for the embedded market. Tilera’s processors are based on a new mesh iMesh™ architecture that scales to hundreds of RISC-based cores on a single chip. The distributed nature of Tilera’s revolutionary architecture and the standards-based tools, such as C/C++ compiler, GNU tools and Eclipse IDE, provide an unprecedented combination of performance, power efficiency and programming flexibility. Tilera was founded in October 2004 and launched its first product, the 64-core TILE64™ processor, in August 2007. The company is headquartered in San Jose, Calif. with locations in Westborough, Mass., Beijing and Bangalore, India.

The BDTI Communications Benchmark (OFDM)™ is a benchmark based on a simplified orthogonal frequency division multiplexing (OFDM) receiver. It is representative of the signal processing workloads found in communications equipment for applications such as DSL, cable modems, and wireless systems. It is designed to enable benchmarking and comparison of a wide range of devices, including processors, FPGAs, and other processing devices, on real-world applications

NVIDIA Edit

http://www.tgdaily.com/content/view/37729/135/ video on chip


Links Edit

WimaxLinks

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