FPGA Camera Interface Using ITU 656 standard

The existing system implements a hardware JPEG encoder attached to a VGA (640x480) CMOS camera running at 30fps. In order to achieve the throughput necessary, each functional block of the encoder will be heavily pipelined, allowing data to be clocked in on every single clock cycle. In order to save hardware, data must be first compressed into JPEG format to reduce the amount of data transmitted. The overall goal is to be able to grab images from an ITU 656 VGA digital video stream and convert each individual frame into a jpeg image at a rate of 30 fps. Figure 1 shows the block diagram of the system.

Figure 1 Block Diagram of camera to FPGA interface using ITU 656

The ITU 656 video will be buffered on the FPGA using vertical and horizontal sync decoding to control a system of FIFOs. These FIFOs will feed pixel macroblocks to DCT module in JPEG encoder. The resulting JPEG file will then be sent over a RS232 serial interface to a computer.

The ITU 656 data stream decoder and FIFO unit takes the 8-bit data stream and data clock as an input and stores them in a set of FIFOs that will eventually feed data to the 8x8 pixel 2-D FDCT. The pixel luminance and two chrominance data words will need to be separated into different FIFOs. The decoder module will need to store eight entire lines of data, this will require eight sets of three 1kb FIFOs resulting in a total of 24kb worth of memory using 24 separate FIFOs. Once the decoder module has stored 8 entire lines of active video, it can then begin passing 8x8 pixel macro-blocks to a set of three 8x8 FDCTs. There are three FDCT modules because the luminance and each of the two chrominance macro-blocks will be processed in parallel to increase the performance of the JPEG encoding process. Each FDCT module sends its result to an independent zig-zag quantizer, where the data is turned back into a stream. After it is put back into a stream, the data is passed to a Huffman Encoder. There are now three separate Huffman-Encoded streams of JPEG data that need to be multiplexed together in the following order, Y-Cr-Cb. Each stream is the result of the compression of one macro-block. The multiplexed data stream is now ready to be sent to the embedded Microblaze processor over the FSL Channel which can be interfaced to the outside world through the RS232 channel.

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